/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`ifndef RISCV_64
`define RISCV_64

`define INST_LOAD			7'b0000011
`define INST_STORE			7'b0100011
`define I_TYPE				7'b0010011
`define IW_TYPE				7'b0011011
`define B_TYPE				7'b1100011
`define R_TYPE				7'b0110011
`define RW_TYPE				7'b0111011
`define INST_JAL			7'b1101111
`define INST_JALR			7'b1100111
`define INST_LUI			7'b0110111
`define INST_AUIPC			7'b0010111
`define	INST_SYS			7'b1110011
`define	INST_NOP			32'h00000013
`define INST_ECALL 			32'h00000073
`define INST_EBREAK			32'h00100073
`define INST_MRET   		32'h30200073

`define FUNCT3_000			3'b000
`define FUNCT3_001			3'b001
`define FUNCT3_010			3'b010
`define FUNCT3_011			3'b011
`define FUNCT3_100			3'b100
`define FUNCT3_101			3'b101
`define FUNCT3_110			3'b110
`define FUNCT3_111			3'b111

`define ZERO				64'h0
`define XLEN                64
`define DXLEN               128
`define DATA_MSB     		63
`define	MEM_ADDR_WIDTH		40
`define CPU_RESET_ADDR		`MEM_ADDR_WIDTH'hfffc
`define	ZERO_ADDR			`MEM_ADDR_WIDTH'h0
`define	ADDR_MSB			39
`define ADDR_LSB            3
`define InstDataBus			31:0
`define	ENABLE				1'b1
`define DISABLE				1'b0
`define	RESET_ENABLE		1'b0
`define	RESET_DISABLE		1'b1
`define RegAddrBus			4:0
`define RegDataBus			63:0
`define	MemAddrBus			`MEM_ADDR_WIDTH-1:0
`define REG_NUM				32
`define REG_ZERO_ADDR		5'h0
`define	ROM_NUM				311296	//	*4=130000 hex
`define	RAM_NUM				1536	//	*8=3000 hex
`define	IrqBus				7:0
`define	IRQ_NONE			8'h0
`define	TrapBus				15:0
`define TRAP_NONE           16'h0
`define ExcBus				7:0
`define	EXC_NONE			8'h0

`define TIMER_BASE          40'h0
`define ROM_BASE            40'h00010000
`define UART_BASE           40'h00140000
`define GPIO_BASE           40'h00150000
`define SDRAM_BASE          40'h00160000
`define ADDR_END            40'h40160000

// CSR reg addr
`define CSR_CYCLE   		12'hc00
`define CSR_MTVEC   		12'h305
`define CSR_MCAUSE  		12'h342
`define CSR_MEPC    		12'h341
`define CSR_MIE     		12'h304
`define CSR_MSTATUS 		12'h300
`define CSR_MSCRATCH 		12'h340

`define IRQ_ASSERT			1'b1
`define IRQ_DEASSERT		1'b0

`define	CACHE_BITS			512
`define	CacheBus			511:0

`endif
